As a method of testing a semiconductor device such as a logic integrated circuit (hereinafter called a “logic IC”) or the like, a method is normally used which generates test pattern data by a device called a tester, inputs it to a logic IC, and compares a data signal outputted from the logic IC with each expected data signal to thereby determine the result of comparison. There is also known a test technology of a BIST (Built In Self Test) type, wherein a pattern generation circuit for generating random test pattern data, like a pseudo-random number generator is built in a semiconductor device. Further, the invention related to a semiconductor memory equipped with a test circuit called an ALPG (Algorithmic Memory Pattern Generator), which is comprised of a microinstruction type controller for generating test patterns (addresses and data) for testing a memory circuit in accordance with a predetermined algorithm and reading data written into the memory circuit, a data operation unit, and a data determining means for determining the data read from the memory circuit and outputting the result of determination, etc. and which is capable of generating a predetermined test pattern in accordance with a built-in program, has been proposed by the present inventors as the technology of testing the semiconductor memory (see International Publication WO98/47152).
FIG. 1 shows a conceptual diagram of a tester regarded as a conventional common tester. As shown in FIG. 1, a tester 100 comprises a power supply unit 110 for supplying a source voltage to a semiconductor device 200 to be tested, a driver 120 for inputting a signal to each input pin of the semiconductor device 200, a comparator 130 for comparing a signal outputted from each output pin of the semiconductor device 200 with an expected data signal, a pattern generator 140 for generating a signal sequence (so-called test patterns) inputted to the semiconductor device 200 and each expected data signal, a timing generator 150 for generating timing provided to apply each signal inputted to the semiconductor device 200, a CPU 160 used as a controller for controlling these circuits. The CPU 160 is configured so as to read a test program from an external storage device and generate and determine a testing signal (so-called test pattern) while interpreting the read test program by means of an OS (Operating System), thereby conducting a predetermined test. The tester 100 might be provided with a DC test circuit 170 for conducting a dc test such as the detection of a voltage level at each output pin.